To edit mesh leakage byte ram in case Can withstand error
File:RAM 8 Byte.png - Wikimedia Commons
Upgraded my 64 Byte RAM memory - it now has 14 tick read, 5 tick write. They delays are equal for all individual cells, meaning the memory is fully synchronised. I'm using
Massimo on X: "1 byte of RAM (1946) vs 32 billion bytes of RAM (2019) https://t.co/qaEg91hHMq https://t.co/aBYEVW0TRB https://t.co/Sut5HfHqjA" / X